1. Field of the Invention
The present invention relates to a CMOS logic circuit, and, more particularly, the invention relates to a CMOS logic circuit with reduced circuit area.
2. Description of the Related Art
Multiple CMOS logic circuits are used in a semiconductor device like a microcomputer or ASIC (Application Specific IC). In accordance with the recent trend of ensuring higher integration of semiconductor devices and reducing power consumption, it is more and more essential to reduce the number of elements and the power consumption of such CMOS logic circuits.